The present invention relates to variable frequency AC motors. More particularly, the present invention relates to an apparatus to eliminate voltage deviations at motor terminals due to switching time delays in pulse width modulated invertors.
One type of commonly designed induction motor is a three phase motor having three Y-connected stator windings. In this type of motor, each stator winding is connected to an AC voltage source by a separate supply line, the source generating currents therein. Often, an adjustable speed drive (ASD) will be positioned between the voltage source and the motor to control motor speed.
Many ASD configurations include a pulse width modulated (PWM) inverter consisting of a plurality of switching devices and a controller for controlling the inverter. Referring to FIG. 1, an exemplary inverter 10 has six switches 12-17. The switches 12-17 are arranged in series pairs, each pair forming one of three inverter legs 39, 40, and 41. Referring to leg 39, by triggering the switches 12, 13 ON and OFF in a repetitive sequence, leg 39 receives DC voltage 18 and provides the high frequency pulses 60 of FIG. 2 to a motor terminal 31. By triggering the switches in a regulated sequence the inverter can be used to control both the amplitude and frequency of voltage that eventually reach the stator windings.
Referring to FIG. 2, an exemplary sequence of high frequency terminal voltage pulses 60 that inverter 10 might provide to a motor terminal can be observed along with an exemplary low frequency alternating fundamental voltage 62 and related alternating current 69. By varying the widths of the positive portions 63 of each high frequency pulse relative to the widths of the negative portions 64 over a series of high frequency voltage pulses 60, a changing average voltage which alternates sinusoidally can be generated. The changing average voltage defines the low frequency alternating voltage 62 that drives the motor. The low frequency alternating voltage 62 in turn produces a low frequency alternating current 69 that lags the voltage by a phase angle.
Referring to FIG. 3(a), representative waveforms used by a signal generator 20 to generate triggering times for leg 39 may be observed. As well known in the art, a carrier waveform 67 is perfectly periodic and operates at what is known as the carrier frequency. A command voltage waveform 68 is sinusoidal, having a much greater period than the carrier waveform 67.
Referring also to FIGS. 3(b) and 3(c), an upper signal 72 and a lower signal 74 that control the upper and lower switches 12, 13 respectively can be observed. The turn-on t.sub.u1, t.sub.u2 and turn-off t.sub.o1, t.sub.o2 trigger times of the upper and lower signals 72, 74 come from the intersections of the command waveform 68 and the carrier waveform 67.
When waveform 68 intersects the carrier waveform 67 while the carrier waveform has a positive slope (i.e. during periods T.sub.p), upper signal 72 goes OFF and lower signal 74 goes ON. On the other hand, when waveform 68 intersects carrier waveform 67 while the carrier waveform has a negative slope (i.e. during periods T.sub.n), upper signal 72 goes ON and lower signal 74 goes OFF. Thus, by comparing carrier waveform 67 to command waveform 68, trigger times can be determined. Signals 72, 74 are provided to the delay module 11.
To implement waveform comparison, typical controllers convert the carrier and command waveforms into times. When command waveform 68 is greater than carrier waveform 67, upper signal 72 is turned ON and when waveform 68 is less than waveform 67, upper signal 72 is turned OFF. Thus, upper signal 72 is ON for a duty cycle during each carrier period T which depends on waveform amplitude A. Amplitude A is normalized to V.sub.bus voltage and is known and therefore an upper signal on-time duty cycle DC corresponding to amplitude A can be derived. Once duty cycle DC is identified, trigger times corresponding to duty cycle DC can be identified.
To determine duty cycle DC the following equation is solved: EQU DC=(A+1/2) Eq. 1
where A is the instantaneous command waveform amplitude. For example, where amplitude A is 0.25, duty cycle DC will be 75%. Where amplitude A is -0.25, duty cycle DC will be 25%.
Waveform 67 is represented by a carrier count signal and a direction signal. For the purposes of this explanation it will be assumed that the carrier count counts up from 0 to 100 when traversing between negative and positive carrier peaks (i.e. during positive carrier waveform slope) and counts down from 100 to zero between positive and negative carrier peaks (i.e. during negative carrier waveform slope).
Upper trigger times can be determined by multiplying duty cycle DC by the maximum carrier count. In the present example the maximum carrier count is 100. Assuming a 75% duty cycle DC, the upper trigger times occur when the carrier count is 75 (i.e. .75*100). In FIG. 3(a), the upper trigger times are illustrated as times t.sub.a and t.sub.b. Times t.sub.a and t.sub.b and the carrier count are provided to a compare register. The compare register compares times t.sub.a and t.sub.b to the carrier count and when the carrier count equals time t.sub.a, upper signal 72 is turned OFF. When the carrier count equals time t.sub.b, upper signal 72 is turned ON.
Referring to FIGS. 1 and 3(d), an ideal high frequency voltage pulse 60 resulting from the upper and lower signals 72, 74 in FIGS. 3(b) and 3(c) that might be provided at terminal 31 can be observed. When upper signal 72 is ON and lower signal 74 is OFF, device 12 allows current to flow from high voltage rail 48 to motor terminal 31 thus producing the positive phase 78 of pulse 60 at motor terminal 31. Ideally, when upper signal 72 goes OFF and lower signal 74 goes ON, device 12 immediately turns OFF and device 13 immediately turns ON connecting motor terminal 31 and low voltage rail 49 producing the negative phase 80 of pulse 60 at motor terminal 31. Thus, ideal high frequency voltage pulse 60 is positive when upper signal 72 is ON and is negative when lower signal 74 is ON.
Ideally, when switch 12 turns on, series switch 13 turns OFF, and visa versa. In reality, however, each switch 12, 13 has turn-on and turn-off times that vary depending on the technology used for their construction. Thus, while signals to turn the upper switch 12 ON and the lower switch 13 OFF might be given at the same instant, the lower switch 13 may go ON faster than the upper switch 12 goes OFF thus providing an instantaneous DC short between a high DC rail 48 and a low DC rail 49. Such a DC short can cause irreparable damage to both the inverter and motor components.
To ensure that the series switches of an inverter are never simultaneously on, delay module 11 modifies the upper and lower signals 72, 74 by adding a turn-on delay period prior to the turn-on times t.sub.u1, t.sub.u2 of each of the upper and lower signals 72, 74. Referring to FIGS. 3(e) and 3(f), the delay periods produce delayed and shortened upper and lower signals 72 and 74 having delayed turn-on times t.sub.u1', t.sub.u2'.
Referring to FIG. 3(g), while the delay periods protect the motor and inverter components, they produce voltage deviations .sub.n at the motor terminal 31 that produce distorted positive and negative pulses 82, 84 and a distorted high frequency voltage pulse 86. These deviations .sub.n can best be understood by referring to FIGS. 1, 2, and 3(e)-3(g).
Referring to FIGS. 1, 2 and 3(e)-3(g), while the terminal current 69 at motor terminal 31 might be positive, the high frequency voltage pulses 60 will be oscillating from positive to negative phase as the delayed upper and lower signals 72', 74' turn the switches 12, 13 ON and OFF. Thus, while the terminal current 69 is positive, two signal states may occur. First, the upper signal 72 may be OFF while the lower signal 74 is ON and second the upper signal 72 may be ON while the lower signal 74 is OFF. Likewise, when the current 69 is negative, the same two signal states may exist.
When the terminal current is positive, and switch 12 is ON while switch 13 is OFF, the high voltage rail 48 is connected to motor terminal 31. Diode 24 blocks the flow of current to the low voltage rail 49. When the upper switch 12 turns OFF at t.sub.o1, both series switches 12, 13 remain OFF during the delay period . As well known in the art, motors have internal inductance. Because of motor inductance, the terminal current 69 caused by the low frequency alternating voltage 62 cannot change directions immediately to become negative each time the high frequency voltage pulse 60 changes from the positive 63 to the negative 64 phase. The current remains positive and diode 24 immediately begins to conduct at t.sub.o1, connecting the low voltage rail 49 to motor terminal 31 as desired. Hence, the terminal voltage goes negative at the desired time t.sub.o1 even though the turn-on time t.sub.u2 of the delayed lower signal 74 does not occur until after the delay period.
On the other hand, when switch 12 is initially OFF and switch 13 is ON and the terminal current 69 is positive, the low voltage rail 49 is connected through switch 13 to motor terminal 31 as desired and the resulting terminal voltage pulse 86 is in the negative phase 84 at terminal 31. When switching device 13 turns OFF at t.sub.o2, as the positive terminal current 69 cannot immediately reverse itself, diode 24 continues to conduct and low voltage rail 49 remains connected to motor terminal 31 for the duration of delay period Thus, during the delay period, instead of having positive phase voltage at terminal 31 as desired, the negative phase 84 of the resulting terminal voltage pulse is extended at terminal 31 until the turn-on time t.sub.u1 of the delayed upper signal 72'.
Comparing FIGS. 3(d) and 3(g), the resulting terminal voltage pulses 86 have wider negative phases 84 and narrower positive phases 82 than the ideal voltage pulses 60. A voltage deviation .sub.n occurs each time the lower switch 13 is turned OFF and the terminal current 69 is positive. The cumulative effect of these voltage deviations .sub.n cause torque irregularities and distort the low frequency alternating fundamental voltage 62 and current 69 of FIG. 2.
A similar type of error is produced when the terminal current 69 is negative and the upper switch 12 turns from ON to OFF. Referring to FIGS. 4(a)-4(c), delayed upper and lower signals 88, 90 and a resulting terminal voltage pulse sequence 92 having errors .sub.p can be compared.
Referring also to FIGS. 1, 2 and 3(a), when the terminal current 69 is negative and the lower signal 90 turns OFF at t.sub.o2 turning switch 13 OFF, diode 23 immediately connects high voltage rail 48 to terminal 31. While both switches 12, 13 are off, the inverter is in a transition state. Thus, at turn-off time t.sub.o2, resultant terminal voltage pulse 92 turns positive as desired. No error results during this switching sequence.
However, when the terminal current 69 is negative and the upper signal 88 turns OFF at t.sub.o1 turning switch 12 OFF, as both switches 12 and 13 are OFF and the terminal current 69 cannot reverse immediately to become positive, diode 23 continues to conduct which connects high voltage rail 48 to terminal 31. Thus, during, instead of connecting to the low voltage rail 49 and going negative as desired, the motor terminal 31 remains connected to the positive rail 48 and the resultant terminal voltage pulse 92 remains positive causing error .sub.p to result.
Referring to FIGS. 2, 3(g), and 4(c), during both negative and positive phases of the terminal current 69, the delay periods produce voltage distorting errors .sub.n and .sub.p. While each individual distortion does not appreciably affect the fundamental alternating voltage, accumulated deviations do distort the alternating voltage. This is particularly true in applications where the frequency of the high frequency pulses is increased because each additional pulse creates an additional deviation. Accumulated deviations produce torque pulsations, reduce fundamental output voltage, and distorted stator winding currents, all of which are undesirable.
One solution to compensate for the deviations is described in U.S. Pat. No. 5,625,550 which issued to the present inventors on Apr. 29, 1997. That patent describes a method for compensating for deviations in the alternating voltage produced by a PWM inverter by allowing error pulses to occur and adjusting the trigger times of inverter switches to compensate for the error pulses. For example, if a specific sequence of trigger times will result in an error pulse which delays a desired pulse by one micro-second, the trigger time sequence is modified such that the specific sequence occurs one micro-second earlier. Then, when the error pulse occurs, the error pulse in conjunction with the modified switching sequence results in a pulse which occurs at the desired time. In this way, the method described in that patent negates the effect of the error pulses.
The U.S. Pat. No. 5,625,550 patent teaches both symmetrical and unsymmetrical methods of modifying pulses. According to the unsymmetrical method only trigger times directly associated with turn on delay errors are modified. However, according to the symmetrical method, associated pairs of trigger times are modified to eliminate delay errors wherein associated pairs of times each consist of an upper switch off time and a follow on time. For example, in FIGS. 3(a) and 3(g), both off time t.sub.a and on time t.sub.b are symmetrically modified to eliminate error .sub.n.
Although a bit more complicated, the symmetrical method is extremely important as many processors cannot modify a trigger time during a carrier waveform period T and must modify signals symmetrically with respect to carrier waveform 67. Processors so limited will be referred to herein as carrier signal centering processors.
While the U.S. Pat. No. 5,625,550 patent teaches advantageous methods, that patent fails to teach or suggest a way to implement unsymmetrical compensation using a typical carrier signal centering processor.
In addition, even where a more sophisticated processor is provided which is capable of implementing unsymmetrical compensation or where a carrier signal centering processor is used to facilitate symmetrical compensation, such compensation taxes the abilities of a typical processor. This is true because most controller processors are bare bones type processors chosen to have only the computing capability required to facilitate typical inverter required processes. For example, typical processors are configured primarily to perform the task of generating command signals in the form of trigger times.
Furthermore, the method of the U.S. Pat. No. 5,625,550 patent can result in terminal voltages which lag commanded voltages by a propagation or lag period. According to the U.S. Pat. No. 5,625,550 patent, after a trigger time is identified, a lag period occurs because the trigger time has to be shifted providing a shifted time and then the trigger and shifted times have to be stored. Next, current polarity and carrier slope have to be identified and used to determine which time, the original trigger time or the modified time, should be selected. Thereafter, time selection takes place and the selected time is passed to the delay module. The resulting trigger time is center aligned with the carrier thus causing a phase shift in the applied motor voltage.
Therefore, it would be advantageous to have an apparatus which, in conjunction with a simple processor, compensates for turn-on delay errors by modifying trigger times of PWM switches to compensate for triggering time errors without overtaxing the controller microprocessor.